(a) Field of the Invention
The present invention relates to a fault diagnosis method for a sequential circuit of an LSI and, more particularly, to a method for localizing a faulty position of a logic circuit by inferring.
(b) Description of the Related Art
A conventional method for localizing a faulty position of an LSI by inferring, as shown in FIG. 1, comprises step 19 of preparing a fault diagnosis dictionary (fault dictionary) using a fault diagnosis simulator (fault simulator), step 20 of obtaining failure information by actually testing an LSI, step 21 of looking up or retrieval of the fault dictionary based on the failure information indicating the results of the test, and step 22 of localizing a faulty position by inferring.
The fault simulator carries out a logic simulation for an LSI while assuming that the LSI includes a faulty position. The fault simulator compares the results of the logic simulation and the expected values of output pins to prepare a fault dictionary in which the assumed faulty position is stored in association with an input fail vector, which has exhibited the fault at the output pin or pins. The fault dictionary is looked up based on the failure information indicating the results of a test which is actually performed for an LSI, thereby enabling possible faulty positions to be inferred. A priority sequence may be assigned among the assumed faulty positions using a plurality of sets of fail/pass information for localizing a faulty position.
In the method as described above, the fault dictionary must be prepared in advance, during which fault simulations must be performed for a prolonged period of time to prepare the fault dictionary for practical use. Accordingly, the method has the problem in that the execution time for the fault simulation is extremely large and the number of data files for the fault dictionary becomes also large as the scale of integration of an LSI to be tested increases.
Further, since the fault model used in the fault simulation is generally designed for a single stacked fault neglecting a floating fail output, that is, single fault assuming "1" or "0" at the fail output, the model does not correctly represent an actual operation in the case of a multiple fault such as a bridge fault. If the model used in the fault simulation is upgraded to cope with such a multiple fault, the method will be impractical, because the execution time required for the fault simulation becomes excessively large.
Another method has been proposed in which the foregoing procedure is repeated in a hierarchical sequence to narrow the suspected area stepwise and which utilizes a procedure for observing the internal circuit of an LSI by an electron beam tester between the procedures so as to limit the suspected area. In this method, starting with a broad area for the procedure, a smaller faulty area assumption is carried out in each stage by limiting the precedent candidate faulty area using the electron beam tester between two of the stages so as to limit the area for the candidate faulty positions before a lower rank of the procedure.
The second method is effective, because the area for candidate fault positions is limited stepwise by observing the candidate fault area. However, this method has a problem in that the observation of an electric potential on an interconnection layer located near the bottom of a multi-level interconnection structure becomes difficult as the number of layers increases due to an increase in the scale of integration of the LSI.